Mnemonic Semantics Encoding
NOP PC = PC + 1 0000 0xxx xxxx xxxx xxxx
BRz <Label> ( Z ) ? PC = PC + 1 + sext(IMM9 offset to <Label>) 0000 1xxx xxxi iiii iiii
BRzp <Label> ( Z|P) ? PC = PC + 1 + sext(IMM9 offset to <Label>) 0001 0xxx xxxi iiii iiii
BRnp <Label> (N | P) ? PC = PC + 1 + sext(IMM9 offset to <Label>) 0001 1xxx xxxi iiii iiii
BRnz <Label> (N|Z ) ? PC = PC + 1 + sext(IMM9 offset to <Label>) 0010 0xxx xxxi iiii iiii
ADD Rd Rs Rt Rd = Rs + Rt 0010 1ddd ddss ssst tttt
SUB Rd Rs Rt Rd = Rs - Rt 0011 0ddd ddss ssst tttt
ADD Rd Rs IMM5 Rd = Rs + sext(IMM5) 0011 1ddd ddss sssi iiii
JSR <Label> R7 = PC + 1; PC = PC + 1 + sext(IMM9 offset to <Label>) 0100 0xxx xiii iiii iiii
AND Rd Rs IMM5 Rd = Rs & sext(IMM5) 0100 1ddd ddss sssi iiii
RTI PC = R7; PSR [15] = 0 0101 0xxx xxxx xxxx xxxx
CONST Rd IMM9 Rd = sext(IMM9) 0101 1ddd ddxi iiii iiii
SLL Rd Rs UIMM4 Rd = Rs << UIMM4 0110 0ddd ddss sssx uuuu
SRL Rd Rs UIMM4 Rd = Rs >> UIMM4 0110 1ddd ddss sssx uuuu
SDRH Rd Rs Rt Rd = Rs >> 1 0111 0ddd ddss ssst tttt
SDRL Rd Rs Rt Rd = {Rs[0], Rt >> 1} 0111 1ddd ddss ssst tttt
CHKL Rs NZP = sign({WORD_SIZE{Rs[0]}}) 1000 0xxx xxss sssx xxxx
DONE Signal to loader that computation is complete 1000 1xxx xxxx xxxx xxxx
SDL Rd = {Rs[WORD_SIZE-1:1], Rt[WORD_SIZE-1]} 1001 0ddd ddss ssst tttt
CHKH Rs NZP = cmp Rs, 0 1001 1ddd ddss sssx xxxx
TCS Rd Rd = (~Rd + 1) 1010 0ddd ddss sssx xxxx
TCDH Rd Rd = (~{Rd,prev} + 1)[2*WORD_SIZE-1:WORD_SIZE] # Rd == Rs, prev insn must be TCS of low bits 1010 1ddd ddss sssx xxxx
ADDC Rd Rs Rd = (Rs + carry) 1011 0ddd ddss sssx xxxx
GCAR Rd Rs Rd = carry 1011 1ddd ddss sssx xxxx
DEC R32-- (external reg needs to be set by DMA) 1100 0ddd ddss sssx xxxx
SFL Float = Rs 1100 1xxx xxss sssx xxxx

Legend
0101 opcode/sub-opcode
ddddestination register
ssssource register 1
tttsource register 2
iiisigned immediate value
uuuunsigned immediate value
xxx"don't care" value
sign(Rs - Rt)+1, 0, or -1, depending on the sign of the subtraction. The registers are treated as signed values.
sign(uRs - uRt)+1, 0, or -1, depending on the sign of the subtraction. The registers are treated as unsigned values. The result of the subtraction is a signed number, despite the inputs being unsigned.
NZPNegative, Zero, and Positive bits from the processor's status register. They are set based on the value of the compare operations, and by any instruction that writes to a register. In the case of registers updating the NZP bits, the value set in the NZP register corresponds to the sign of the value written to the register (+1, 0, -1).